A device and a method for performing high-speed low overhead context switch, and especially a device and a method for performing high-speed low overhead context switch in a processor that allows multilevel nested interrupts and exceptions.
Most processors have a central processing unit (i.e.xe2x80x94CPU) that is coupled to a register file. The central processing unit is also commonly referred to as an arithmetic logic unit ALU. A processor handles tasks, whereas a task is an independent thread of control. Associated with any task is a task context. A task context is the information that a processor needs needs in order to define the state of the associated task and enable its continued execution. Usually, a task context includes the content of the general purpose registers that the task uses, the task""s program counter and program status information. A task context is stored in a register file accessed by the CPU.
A processor handles a task until the task ends or until the processor is requested to handle a higher priority task. The task is halted and the processor performs a context switch that enables the processor to handle the higher priority task. Usually, interrupts and exceptions are given relatively high priority.
In some prior art solution, during a task switch the task context was transferred to an internal or an external memory module. The task context is retrieved from the internal or external memory module after the processor finishes to handle the higher priority task.
A relative high overhead is associated with some of the prior art methods for performing a context switch. Such a prior art solution is implemented in the TriCore architecture of Siemens. The register file used in the TriCore architecture is partitioned to two halves that are referred to as an upper context and a lower context. The TriCore has a plurality context save areas (CSA) within a memory module. Each CSA can store the upper context or the lower context. The various CSAs are linked to each other. The processor can not start to handle a higher priority task until at least the lower context is transferred to a CSA. This solution is time consuming and results in a relatively high overhead.
Motorola M*Core chip has a very low overhead context switch capability for real time event handling. The M*Core chip has two register files. A general register file and an alternate register file. The alternate register file reduces the overhead associated with context switching and saving/restoring time for critical tasks. When selected, the alternate register file replaces the general register file for all instructions that normally use a general register. Important parameters and pointer values may be retained in the alternate file and thus are readily accessible when a high priority task is entered. The M*Core is very effective when a there are up to two priority levels. Two priority levels indicate that in each given moment there are up to two relevant contextsxe2x80x94a lower priority task context and a higher priority task context. The first can be stored in the general register file while the second can be stored in the alternate register file. Therefore, the context switch does not require any context to be written to a memory module. Thus, the two register files of the M*Core allow very low overhead context switching capability for real time events.
The complexity of CPU and especially the variety of tasks that they handle has grown in the last years. Processors are required to support multilevel nesting of tasks. Prior art methods and devices did not have a high speed low overhead context switch capability for supporting multilevel ( greater than 2) nesting of tasks.
There is a need to provide a device and a method for performing fast context switching with very low overhead, in processors that support multilevel nesting of tasks.